ORAN Hardware projects on GitHub are designed to demonstrate different use cases on ZCU102 or ZCU111 boards. This blog will show you how to generate the design and use the API to configure your CC settings after the board is booted. Hardware Design Architecture Design generation PTP test setup board2board PTP test Third party O-DU […]
The example design is created in the 2020.2 version of Vivado, targeting a VCK190 evaluation board. Interrupts are tested on PetaLinux 2020.2, and the design Tcl and system-user.dtsi file are attached.Use MATLAB ® and Simulink ® to develop, deploy, and verify wireless systems designs on Xilinx ® Zynq ® UltraScale+™ RFSoC devices.. Characterize RF performance with data streaming between hardware and MATLAB and Simulink. Leverage standards-compliant (5G and LTE) and custom waveforms.
Xilinx's Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit enables designers to jumpstart RF-Class analog designs for wireless, cable access, early-warning (EW)/radar, and other high-performance RF applications. This kit features a Zynq UltraScale+ RFSoC supporting eight 12-bit 4.096 GSPS ADCs, eight 14-bit 6.554 GSPS DACs, and eight soft ...Messages by Thread [casper] FASR2021 Workshop Jonathon Kocz [casper] ZCU111 100GbE Example Available Now Jenny Smith [casper] SKARAB wideband spectrometer tutorial(s) Mathews Chirindo [casper] Massive In-Network Processing for the World's Largest Radio Telescope (SKA-Low) Adam Isaacson [casper] Tips to speed up simulation Sebastian Antonio Jorquera Tapia